This invention relates to a phase difference detecting unit which is applied to an automatic focus detector for a camera.
A conventional automatic focus system employing a phase difference detection method is shown in FIG. 8. A condenser lens 3, a separator lens 4, and a phase difference detecting unit 8 are positioned behind a plane 2, which is equivalent to the surface of a film and is located behind the photographing lens 1 of a camera (not shown).
The phase difference detecting unit 8 consists of linear image pickup devices 5 and 6, which receive a pair of optical images of an object (not shown) formed by the separator lens 4. The pickup devices subject the images to photo-electric conversion. A correlation operating circuit 7 determines whether or not the lens 1 is focused. This determination is made from picture element signals which are produced in accordance with luminance distributions of devices 5 and 6.
The images formed on the image pickup devices 5 and 6 are moved towards the optical axis when the object's image is located in front of the equivalent plane 2. This is referred to as a front focusing condition. The images are moved away from the optical axis in the rear focusing condition. When the lens is properly focused, the images come to predetermined positions which are located between these positions taken in the front focusing condition and those taken in the rear focusing condition. Hence, the correlation operating circuit 7 can determine whether or not the lens is correctly focused on the object. More specifically, the circuit 7 performs a correlation operation for the picture element signals outputted by the linear image pickup devices to detect the relative distances of the images from the optical axis. In this manner, the correlation operating circuit 7 determines whether or not the correct focusing condition is obtained.
The above phase difference detecting method will be described in more detail below. The picture element signals are outputted by the linear image pickup devices 5 and 6 with predetermined synchronizing timing and can be represented by signals R(t) and B(t), respectively (as shown in FIG. 8). The relative shift (amount of relative movement) of these picture element signals can be represented by L. In the detecting method, a correlation operation is performed in accordance with equation (1) below, to obtain a correlation value H(L). With a predetermined amount of movement L.sub.1, it is determined that the correct focusing condition is attained when the correlation value is minimum (or maximum). When, with an amount of movement L.sub.2 different from the predetermined amount of movement L.sub.1, the correlation value is maximum (or minimum), it is determined that the front focusing condition (or the rear focusing condition) is obtained. In addition, the error per unit .DELTA.L provided until the correct focusing condition is obtained is estimated from (L.sub.2 -L.sub.1)/H(L), where ##EQU1## and where n is the number of picture element, and L is an integer variable ranging from 0 to 10.
Heretofore, the above-described correlation operation is carried out with a digital operation device, such as a microprocessor, with the output picture element signals of the linear image pickup devices 5 and 6 converted into digital data. However, the method is disadvantageous in that a circuit large in scale and intricate in arrangement is required for implementation. Moreover, the speed of the arithmetic operation is relatively slow.
In order to overcome these difficulties, an analog correlation operation circuit has been proposed, for instance, by Unexamined Japanese Patent Application No. 229211/1990, as shown in FIG. 9.
In this circuit, signals R(t) and B(t) are outputted in a time-series mode by the linear image pickup devices 5 and 6 (FIG. 8) and are applied to input terminals P.sub.r0 and P.sub.b0, respectively. The input terminal P.sub.r0 is connected to the inverting input terminal (-) of differential amplifier 10 through a buffer amplifier and a series circuit consisting of a switching element 8, a capacitive element C.sub.s1, and a switching element 9. Both terminals of the capacitive element C.sub.s1 are grounded through switching elements 11 and 12. Similarly, the input terminal P.sub.b0 is connected to the non-inverting input terminal (+) of differential amplifier 10 through a buffer amplifier and a series circuit composed of a switching element 13, a capacitive element C.sub.s2, and a switching element 14.
Both terminals of the capacitive element C.sub.s2 are grounded through switching elements 15 and 16. A parallel circuit composed of a capacitive element C.sub.1 and a switching element 18 is connected between the inverting input terminal and the output terminal 17 of the differential amplifier 10, the non-inverting input terminal of the amplifier 10 being grounded.
The input terminals P.sub.r0 and P.sub.b0 are further connected to the non-inverting and inverting input terminals of analog comparator 19, respectively. The output terminal of the comparator 19 is connected to channel select circuit 20.
The channel select circuit 20 provides select signals .epsilon..sub.1, .epsilon..sub.2, KA and KB to control the on-off operations of the switching elements 8, 9, and 11 through 16.
Analog comparator 19 outputs a signal S.sub.gn having a high ("H") level when R(t).gtoreq.B(t) and a low ("L") level when R(t)&lt;B(t). Channel select circuit 20 determines the voltage levels of the select signals .epsilon..sub.1, .epsilon..sub.2, KA and KB in accordance with the levels of the signal s.sub.gn.
The operation of the arithmetic unit organized as described above will now be described with reference to the timing chart of FIG. 10.
First, switching element 18 is turned on with a reset signal .epsilon..sub.RST from a reset device (not shown). As a result, the capacitive element C.sub.1 is discharged. Thereafter, the switching element 18 is turned off so as to start the operations shown in FIG. 10.
When the relationship between the operated signals is R(t).gtoreq.(B(t), as shown in the period between times t.sub.1 and t.sub.2, the signal S.sub.gn is at "H" level. In accordance with signal S.sub.gn, the select signals .epsilon..sub.1, .epsilon..sub.2, KA and KB are produced with a predetermined timing scheme. More specifically, the select signals .epsilon..sub.1 and .epsilon..sub.2 are produced in such a manner that they are not raised to "H" level at the same time, and similarly the select signals KA and KB are produced in such a manner that they are not raised to "H" level at the same time.
In the case where R(t)&lt;B(t) is established, as shown in the period between times t.sub.3 and t.sub.4, the signal S.sub.gn is set to "L". The select signals KA and KB are produced in opposite phase relative to the signals KA and KB set in the period of time marked by t.sub.1 and t.sub.2. The select signals .epsilon..sub.1 and .epsilon..sub.2 are produced with the same timing scheme in either of the periods marked by t.sub.1 -t.sub.4, irrespective of the level of the signal S.sub.gn.
In the first half T.sub.F1 of the period between times t.sub.1 and t.sub.2, switching elements 12 and 16 and switching elements 8 and 15 are turned on due to select signals .epsilon..sub.1, .epsilon..sub.2, KA and KB; thus, capacitive element C.sub.s1 is charged by the signal R(t), while the capacitive element C.sub.s2 is discharged (FIG. 9).
In the second half T.sub.R1 during the period between times t.sub.1 and t.sub.2, the switching elements 9 and 11 are turned on, so that the charge of the capacitive element C.sub.s1 is coupled to the charge of the capacitive element C.sub.1. At the same time, the switching elements 13 and 14 are tuned on, while the switching elements 15 and 16 are turned off. This allows the signal B(t) to be supplied through the capacitive element C.sub.s2 to the differential amplifier 10. As a result, the charge q(t) defined by equation (2) below is stored in capacitive element C.sub.1. EQU q(t)=(C.sub.1 /C.sub.s1).times.R(t)-(C.sub.1 /C.sub.s2).times.B(t)(2)
when R(t)&lt;B(t) during the first half T.sub.F2 of the period between times t.sub.3 and t.sub.4, the switching elements 11 and 13 and the switching elements 12 and 16 are tuned on, so that the capacitive element C.sub.s2 is charged by signal B(t), while the capacitive element C.sub.s1 is discharged. In the second half T.sub.R2 of the same period of time, the switching elements 14 and 15 are turned on, and the charge of the capacitive element C.sub.s2 is added to the charge of the capacitive element C.sub.1. At the same time, the switching elements 8 and 9 are turned on while the switching elements 11 and 12 are turned off, so that the signal R(t) is supplied through the C.sub.s1 to the differential amplifier 10. As a result, the charge q(t) represented by equation (3) below is stored in the capacitive element C.sub.1 : EQU q(t)=(C.sub.1 /C.sub.s2).times.B(t)-(C.sub.1 /C.sub.s1).times.R(t)(3)
As is apparent from the above-described equations (2) and (3), the arithmetic unit As operative to cause the charge corresponding to the correlation value to be stored in the capacitive element C.sub.1. The value is obtained by subtracting one of the signals R(t) or B(t), whichever is lower in level, from the other. Therefore, by repeatedly carrying out the above-described arithmetic operation with respect to the operated signals R(1), . . . and R(n) and B(1) through B(n), the sum of the absolute values of the differences between these signals is provided at the output terminal 17; that is, a correlation value H represented by equation (4) below is output. ##EQU2##
Next, the signals R(t) and B(t) are read from the linear image pickup devices 5 and 6 with a phase difference, and, with respect to the signals thus read, the above-described arithmetic operation is carried out, so that, with respect to the phase difference a correlation value is obtained. Similarly, the correlation operation is performed with respect to other phase differences. As a result, the distribution of correlation values corresponding to the above-described equation (1) is obtained. The correct focusing condition can, thereby, be determined from the distribution.
A phase difference detecting circuit based on the above-described analog correlation operation is advantageous in that it is capable of operation or at least high speeds. However, as the speed is increased, the accuracy of the operation greatly decreases. Specifically, when the operations of the switching elements affect the capacitive loads connected to the input terminals P.sub.r0 and P.sub.b0, the voltages at the inverting and non-inverting input terminals of the analog comparator 19 are changed. Accordingly the voltage at the output terminal S.sub.gn of the analog comparator 19 is also changed. Hence, the on-off control of the switching elements is not correctly carried out, which decreases the accuracy of the correlation result obtained.
In the case where buffer amplifiers having large output current capacities are connected to the input terminals P.sub.r0 and P.sub.b0, the circuit is unavoidably bulky. Accordingly, the consumption of current is increased while the quantity of heat generated is increased.